1. Field of Invention
The present invention relates generally to a semiconductor device and a method of manufacturing the same and, more particularly, to a three-dimensional non-volatile memory device, a memory system including the same and a method of manufacturing the same.
2. Related Art
A non-volatile memory device retains data even in the absence of a power supply. Two-dimensional memory devices in which memory cells are fabricated in a single layer over a silicon substrate are reaching physical limits, preventing higher levels of integration. Accordingly, three-dimensional non-volatile memory devices in which memory cells are stacked in a vertical direction over a silicon substrate have been proposed.
FIG. 1 is a cross-sectional view illustrating the structure of a conventional three-dimensional structured non-volatile memory device.
As shown in FIG. 1, the conventional three-dimensional (3D) structured non-volatile memory device may include a plurality of memory cells MC stacked along channels CH that protrude from the substrate 10. The memory cells MC may be coupled in series between a lower select transistor LST and an upper select transistor UST, thus forming a single string. In addition, the conventional 3D structured non-volatile memory device may include bit lines BL that are coupled to the channels CH.
In FIG. 1, gate insulating layers are denoted by “11” and “16,” lower select lines are denoted by “13,” word lines are denoted by “15,” and upper select lines are denoted by “17.” In addition, an interlayer insulating layer is denoted by “12,” which may generally comprise of an oxide layer.
Since the interlayer insulating layer between cells of the conventional 3D structured non-volatile memory device comprises of an oxide layer, there may be excessively high capacitance (A) between the word lines, which may increase the time taken for cells to be programmed.